![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png){kind=small}
Marriage of duct tape...
Jan. 4th, 2018 07:36 amThis post will start the documention on what I needed to do to get HDL Designer to run with the Xilinx Coregen component libraries (maybe the Microblaze processors as well, we shall see...).
For posterity's sake (and in case my config gets trashed), my HDL Designer setup is as follows (go to "Help->HDS Setup Assistant..."):
I think that's enough for this post, and I will maybe post more on creating the rest of the design if I think anything isn't working intuitively (and that someone else might benefit from my frustrations).
- Target board: Digilent Atlys, Spartan 6 FPGA, LX45, 324-pin BGA, speed -3 (from Reference Manual); Mentor Graphics HDL Designer 2015.1; Xilinx ISE 14.7; CentOS 7 GNU/Linux operating system.
- Click on FPGA Technology Setup per the instructions in the AppNote 10053, "Designing with Xilinx's Coregen Components within HDL Designer" (good luck in finding it, I apparently got lucky somehow). Enter in the information on the FPGA in question [note, I had already set up the workflow for Xilinx ISE and ModelSim], the package is csg324 (presumably since it's the only 324 pin package), and the device is "6slx45". Click on the FPGA Libraries "Compile/Update" button.
- And here's where everything tanks [Note: under "Options->Main...->User Variables", I have task_ModelSimPath set to "/opt/ModelSim/modeltech/bin"]. Apparently even if one selects VHDL as the language and gives "-64bit" in the"Additional VHDL options:" field, HDL Designer steadfastly refuses to append it and the compilation fails. Luckily for me this time, I spent weeks figuring out what to do last year and don't have to repeat that very painful experience. Pro tip: if you want to see the command line used for compilation and all the messages (if you launch it from HDL Designer) from the compiler, look for the compxlib.log files in the hierarchy of the destination directories.
- On the command line, I use can use the following to compile the libraries successfully: "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/compxlib -arch spartan6 -dir /home/pheloniusfriar/projects/itk/compiled_libs -l all -lib all -s mti_se -p /opt/Xilinx/ModelSim/modeltech/bin -64bit -w". The destination directory "-dir ..." is just where I decided to keep the compiled libraries. You can make your own mistakes ;). There's a tolerable guide for compxlib in the Xilinx "Command Line Tools User Guide" [my version is UG628 (v14.7)], Chapter 25, but the -l is languages, -lib is which libraries to compile, and -w is to overwrite any already compiled libraries (just in case in my case, but I started with an empty "compiled_libs" directory). Be patient, the Embedded Design Kits (EDK) especially takes a long time.
- Once the libraries are compiled manually, in the "FPGA Vendor Library Compilation" window (opened by the "Compile/Update" button), click ON the "Create Library Mapping Only (No Compilation)" button, leave OFF the "Create Library Mapping in Shared Project" button, and turn on the "Import Unisim Library for Instantiating in Designs", use "Custom Location" and browse to where the destination directory for the manually compiled libraries (in the box, it shows up for me as "$HDS_PROJECT_DIR/../../compiled_libs/"). In my case I also want to include the Cores and Embedded CPUs libraries, so I have turned ON the "Include Vendor Primitives and Core Libraries" and "Include Embedded Design Kits (MicroBlaze, PowerPC)" buttons, and then in the "Compiled Vendor Library Path" box, I have the "edk" subdirectory of the destination directory for the manually compiled libraries (shows up as "$HDS_PROJECT_DIR/../../compiled_libs/edk" in my case).
- Click on the "Run" button and ... the library linkages are done! Press "OK" on the "FPGA Technology Setup" window to set the device you're using.
- If everything is set up correctly, double-clicking on the Xilinx CORE Generator task should launch the "Xilinx CORE Generator Interface" window. All the defaults should be okay (they were for me), and clicking on the "Invoke CORE Generator..." button launched the actual Xilinx CORE Generator tool!
- Generate cores... :). In my case, I want to create an Ethernet interface.
For posterity's sake (and in case my config gets trashed), my HDL Designer setup is as follows (go to "Help->HDS Setup Assistant..."):
- Language-> For graphical descriptions: VHDL 2008; For VHDL text descriptions: VHDL 2008; For Verilog text descriptions: System Verilog.
- Type of Design-> What type of design do you want to create? FPGA; Do you want to use any of the following technology libraries? Xilinx.
- Simulator->"New Simulator...". Chose ModelSim in my case (could have used QuestaSim I guess, I have access to it as well, but don't know better one way or the other and ModelSim was the first one I had, so...). Click on "Browse..." to select a "directory that contains the executable for ModelSim". In my case, I had to point to "/opt/ModelSim/modeltech/bin".
- Synthesis-> "Xilinx Synthesis (/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64)" is selected. [I think it was automatically presented because I source the Xilinx config before running HDL Designer, ". /opt/Xilinx/ISE_DS/settings64.sh"].
- Other Flows-> HDL Generation from C/C++: yes; I/O Designer (not shipped with HDS): yes [don't remember doing this, but there you have it... they do show up in "My Tasks" in the Design Manager].
- Version Management-> Disabled [at this stage, it's one more thing to bang my head against... when I start working for real, I will get it running for sure].
I think that's enough for this post, and I will maybe post more on creating the rest of the design if I think anything isn't working intuitively (and that someone else might benefit from my frustrations).
