PSoC Processors and Infineon
Jun. 8th, 2022 09:45 amI like PSoC processors, and I cannot lie. They were extremely innovative and the development tools are like nothing else in the industry. In specific, these are "system on a chip" chips that actually live up to their name: they have a CPU (either an 8051 variant or some flavour of ARM processor... the PSoC 4200 that I have been using often has a 48MHz ARM Cortex-M0+ CPU), a fairly complete set of often-used peripherals (e.g. Serial Communications Blocks that can be a UART, I2C, SPI, etc.), but then they have programmable and reconfigurable digital and analog circuitry! On the analog side, it comes with things like op-amps, comparators, multiple-input scanning ADCs, and DACs (some specialized current mode ones for use with capacitive touch sensing, another specialty of the PSoC processors), and the PSoC 1 had support for switched capacitor technologies (used for signal filters, etc.). But it was routable on the chip and could be connected to almost any pin (there were "associated" pins that used less resources, but it wasn't cast in stone that they had to be used)! For the digital side of things, they created something called Universal Digital Blocks (UDBs). I'm not going to lie... UDBs are hard to use and it takes a lot of work to wrap your brain around them... but, once (if?) you figure out how to use them... wow! Like seriously wow, these things are game changing! Where in most designs I would need to add all sorts of circuitry to a board to customize it to the application I want to use it for, with UDBs I could implement most smallish designs right on the PSoC chip itself without having to use any other chips on the printed circuit board to support the application. I can't emphasize too hard how spectacular this capability is. Without going into detail (I could go on and on, but won't), the UDBs each contain two PLDs (12C4 with 8 product terms (PTs)), a swiss army knife control and status block (so many different functions), all the digital and clock and reset programmable routing needed, and an 8-bit "datapath processor" (DP) that can be chained to adjacent DPs to form larger data-word processors (e.g. 32-bit). The microcode of the DP processor is normally controlled by the PLD logic... you can literally build your own custom processor out of programmable logic on the PSoC itself from UDBs. The DP contains an ALU, a register set, input and output FIFOs (to communicate with the CPU and optional DMA on some chips), and an 8 instruction microcode set (surprisingly powerful). UDBs can also be used to build things like " I2C, UART, SPI, SDI12 , OneWire, (Capture) Timer block, CAN, Manchester decoder, Quadrature decoder, Counter block, SmartIO, LFSR / CRC functionality, ShiftReg glitch filtering, State Machine functionality, and random number generation". Powerful, but hard to work with because of their configurability and layer upon layer of functionality. The PSoC chips contain zero to dozens of these UDBs, and the 4200 that I've gravitated to has 4.
Cypress, who made the PSoC family, was bought by Infineon, and I don't know what I'm seeing yet. Even before then, Cypress seemed to be moving away from the "system on chip" concept, that made them stand out in the crowded and competitive microcontroller field, towards more ultra high volume applications with hardcoded functionality on their processors rather than the configurable logic and analog capabilities that made PSoC different. In one of the forums, someone [Rolf_Nooteboom] said (before the Infineon buyout) "I am still worried Cypress is phasing out UDBs and that would be worst thing what could happen to PSoC imho (it would then be like any other microcontroller and lose a lot of the functionality for why one would choose PSoC over an other MCU)", to which someone [Len_CONSULTRON] answered "According to a Field rep for Cypress I spoke to, this appears to be the direction. It is my understanding that the reasoning behind this direction is that few designers using their product make use of all the UDB and routable analog features". By the very nature of having a reconfigurable digital and analog feature set, the functionality built onto the chip will always be a superset of what is used in any particular application (although I've come close to using every part of a PSoC in one application). This "wastage" means we're paying for circuitry on the chip that is not used. The cost/benefit equation is such that the hope is that extra cost is more than offset by speeding development (saving money on R&D directly, but also by getting to market faster which can easily be a 50% increase in profits) and reducing parts count on the printed circuit board (fewer components means less costly boards and lower board R&D costs, higher reliability, and lower inventory/stock requirements which can also be huge [especially in times of supply chain disruptions like we're seeing now]). This value proposition doesn't break down until very high volumes are achieved with product sales (like hundreds of thousands to millions of units of one design). The margins get slimmer for chip manufacturers as volumes increase, but so does the challenge of having to manage a complex product portfolio where a few models get chosen for a few high volume products and the rest end up in medium to low volume applications. Here we see another sickness caused by the MBA/CEO class: they're lazy and stupid and are obsessed with specific metrics that translate into short term success (where they fill their pockets) but not into long term company stability (if the horses they were betting on fail, there's nothing to fall back on... saw it at Nortel before it went bust... it's the same sort of people every time: they ditch the product lines growing at 5% a year in favour of the latest bubble growing at 100% per year, and when the bubble collapses, so does the whole company... but I digress).
Anyway, there are two reasons why I'm making this post. The first is that I'm working on a design that has ended up needing quite a bit of UDB functionality, and the second is that I commented on the above forum discussion with the following, which I wanted to preserve for myself (in case Infineon nukes the community forums or specific threads... although they do seem to be enhancing them rather than shutting them down, although there was a definite period of chaos that was quite concerning).
UDBs and analog routing are the reason why I've stuck with PSoC even though it's a more expensive chip in some cases: the per-unit cost is made up for by the integration, ease of use, and flexibility it offers me as a designer (not to mention the uniqueness of PSoC Creator!). The patents look like they're in place (depending on which one) for the next decade or so. If Infineon/Cypress does phase out UDBs, I hope someone licenses those patents to use them in their own chips (or that they sell at least some of the "before PSoC 6" families to another company). If not, in 2032 (presuming they're not abandoned earlier), someone could integrate them, or an upgraded version of them (I can think of some changes that would be great), into RISC-V based chips perhaps or as dedicated "configurable/programmable datapath" chips (in either case, the clock rates could probably be jacked up significantly).
The two main relevant patents I could find are:
Universal digital block with integrated arithmetic logic unit
Universal digital block interconnection and channel routing
I'd love to have the money to make an offer to buy the PSoC line (or at least some sub-technologies like the UDB), but I live from paycheque to paycheque (and not always reliably) like many people. So file the thought under "if wishes were fishes".
Anyway, more of a "note to self" than anything.
On an unrelated note, I managed to finish "Season 1" of "The Passionate Friar on YouTube" (Episode 26). It ends with a bang and not a whimper (intensity 11 out of 10), and I am doing some "housekeeping" before starting on "Season 2" (hopefully some time in the next 8 weeks).
Cypress, who made the PSoC family, was bought by Infineon, and I don't know what I'm seeing yet. Even before then, Cypress seemed to be moving away from the "system on chip" concept, that made them stand out in the crowded and competitive microcontroller field, towards more ultra high volume applications with hardcoded functionality on their processors rather than the configurable logic and analog capabilities that made PSoC different. In one of the forums, someone [Rolf_Nooteboom] said (before the Infineon buyout) "I am still worried Cypress is phasing out UDBs and that would be worst thing what could happen to PSoC imho (it would then be like any other microcontroller and lose a lot of the functionality for why one would choose PSoC over an other MCU)", to which someone [Len_CONSULTRON] answered "According to a Field rep for Cypress I spoke to, this appears to be the direction. It is my understanding that the reasoning behind this direction is that few designers using their product make use of all the UDB and routable analog features". By the very nature of having a reconfigurable digital and analog feature set, the functionality built onto the chip will always be a superset of what is used in any particular application (although I've come close to using every part of a PSoC in one application). This "wastage" means we're paying for circuitry on the chip that is not used. The cost/benefit equation is such that the hope is that extra cost is more than offset by speeding development (saving money on R&D directly, but also by getting to market faster which can easily be a 50% increase in profits) and reducing parts count on the printed circuit board (fewer components means less costly boards and lower board R&D costs, higher reliability, and lower inventory/stock requirements which can also be huge [especially in times of supply chain disruptions like we're seeing now]). This value proposition doesn't break down until very high volumes are achieved with product sales (like hundreds of thousands to millions of units of one design). The margins get slimmer for chip manufacturers as volumes increase, but so does the challenge of having to manage a complex product portfolio where a few models get chosen for a few high volume products and the rest end up in medium to low volume applications. Here we see another sickness caused by the MBA/CEO class: they're lazy and stupid and are obsessed with specific metrics that translate into short term success (where they fill their pockets) but not into long term company stability (if the horses they were betting on fail, there's nothing to fall back on... saw it at Nortel before it went bust... it's the same sort of people every time: they ditch the product lines growing at 5% a year in favour of the latest bubble growing at 100% per year, and when the bubble collapses, so does the whole company... but I digress).
Anyway, there are two reasons why I'm making this post. The first is that I'm working on a design that has ended up needing quite a bit of UDB functionality, and the second is that I commented on the above forum discussion with the following, which I wanted to preserve for myself (in case Infineon nukes the community forums or specific threads... although they do seem to be enhancing them rather than shutting them down, although there was a definite period of chaos that was quite concerning).
UDBs and analog routing are the reason why I've stuck with PSoC even though it's a more expensive chip in some cases: the per-unit cost is made up for by the integration, ease of use, and flexibility it offers me as a designer (not to mention the uniqueness of PSoC Creator!). The patents look like they're in place (depending on which one) for the next decade or so. If Infineon/Cypress does phase out UDBs, I hope someone licenses those patents to use them in their own chips (or that they sell at least some of the "before PSoC 6" families to another company). If not, in 2032 (presuming they're not abandoned earlier), someone could integrate them, or an upgraded version of them (I can think of some changes that would be great), into RISC-V based chips perhaps or as dedicated "configurable/programmable datapath" chips (in either case, the clock rates could probably be jacked up significantly).
The two main relevant patents I could find are:
Universal digital block with integrated arithmetic logic unit
Universal digital block interconnection and channel routing
I'd love to have the money to make an offer to buy the PSoC line (or at least some sub-technologies like the UDB), but I live from paycheque to paycheque (and not always reliably) like many people. So file the thought under "if wishes were fishes".
Anyway, more of a "note to self" than anything.
On an unrelated note, I managed to finish "Season 1" of "The Passionate Friar on YouTube" (Episode 26). It ends with a bang and not a whimper (intensity 11 out of 10), and I am doing some "housekeeping" before starting on "Season 2" (hopefully some time in the next 8 weeks).